From: Andrew Cooper Date: Wed, 22 May 2013 13:26:52 +0000 (+0200) Subject: AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail pointers X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~6797 X-Git-Url: https://dgit.raspbian.org/%22http:/www.example.com/cgi/%22https:/%22bookmarks://%22Dat/%22http:/www.example.com/cgi/%22https:/%22bookmarks:/%22Dat?a=commitdiff_plain;h=6d243308e1d75f866679db226159c797d6c83aad;p=xen.git AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail pointers Reference at time of patch: http://support.amd.com/us/ChipsetMotherboard_TechDocs/46303.pdf Erratum 64 states that the head and tail pointers for the Command buffer and Event log are only reset on a cold boot, not a warm boot. While the erratum is limited to systems using SR56xx chipsets (such as Family 10h CPUs), resetting the pointers is a sensible action in all cases, including the PPR log for consistency. Signed-off-by: Andrew Cooper Acked-by: Keir Fraser Acked-by: Suravee Suthikulpanit --- diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c index abb94ece54..0bcf8d2025 100644 --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -154,6 +154,11 @@ static void register_iommu_cmd_buffer_in_mmio_space(struct amd_iommu *iommu) IOMMU_CMD_BUFFER_LENGTH_MASK, IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry); writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET); + + /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen + * automatically for us. */ + writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET); + writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET); } static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu) @@ -182,6 +187,11 @@ static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu) IOMMU_EVENT_LOG_LENGTH_MASK, IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry); writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET); + + /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen + * automatically for us. */ + writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET); + writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET); } static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu) @@ -210,6 +220,9 @@ static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu) IOMMU_PPR_LOG_LENGTH_MASK, IOMMU_PPR_LOG_LENGTH_SHIFT, &entry); writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET); + + writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET); + writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET); }